Title :
Development of second-level connection method for large-size CPU package
Author :
Baba, S. ; Koide, Masateru ; Watanabe, Manabu ; Fukuzono, Kenji ; Yamamoto, Takayuki ; Sakuyama, Seiki ; Shimizu, Kazuo ; Okamoto, K. ; Mizutani, Daisuke
Author_Institution :
Fujitsu Adv. Technol. Ltd., Kawasaki, Japan
Abstract :
This paper reports on second-level interconnection development for a large-scale Ball Grid Array (BGA) package. Generally, control of warpage becomes a problem as BGA packages become larger. To solve this problem, the following two measures were executed. The first was adoption of a low-temperature solder, and the second was warpage control using a heat spreader as a fixture. We were able to decrease the reflow temperature to 200°C by applying the low-temperature solder, and the effect was a warp reduction of 200 μm. Moreover, the shape of the heat spreader was optimized through a thermal-stress simulation, obtaining a warp reduction of 100 μm. Verification with a test vehicle was executed, no short/opening was observed, and the results of a thermal cycle test and simulation confirmed there was no problem in reliability.
Keywords :
ball grid arrays; heat sinks; reflow soldering; thermal management (packaging); thermal stresses; BGA package; heat spreader; large-scale ball grid array package; large-size CPU package; low-temperature solder; reflow temperature; second-level connection method; size 100 mum; size 200 mum; temperature 200 C; thermal cycle test; thermal-stress simulation; warp reduction; warpage control; Cooling; Heating; Pins; Reliability; Strain; Substrates;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location :
Orlando, FL
DOI :
10.1109/ECTC.2014.6897269