SNM-aware power reduction and reliability improvement in 45nm SRAMs

Read stability and write ability are important factors in SRAM design. However, read stability and write ability of the 6T-cell are conflicting design requirements. It is increasingly more difficult to balance these requirements with conventional transistor sizing and V_th optimization as technology scales. In this paper, we present a method to help reduce SRAM power consumption by deciding the optimal pull-up transistor size in 6T SRAM cell. Our experiments show that the proposed method can reduce the supply voltage as much as 7-8%. Furthermore, our method has an average 7.76% power reduction in both active and standby mode at 25°C, a 35% V_th variation reduction, 7.78% SNM variation reduction and 11.3% NBTI degradation reduction with at most 1.95% area overhead.