Title :
On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system
Author :
Xie, Jing ; Xing, Huimin ; Mao, Zhigang
Author_Institution :
Sch. of Microelectron., Shanghai Jiaotong Univ., Shanghai, China
Abstract :
High throughput and high computation many core based on chip architecture is a development trend for high performance digital signal processing platform design. With frame and block data processing technology feature, the general linear memory architecture and on chip interconnection scheme may cause performance bottleneck for the application. In this paper work, we propose a 64-core array on chip architecture for high throughput and high performance 2-D block data processing, which with the features of hierachical architecture level, mirror symmetric interconnection structure and a Block level 2-D data addressing scheme. From the experiment show, the design can meet real time processing requirement of the 1080P data frame from H.264/AVC specification by use of block level matrix computation with average dynamic power report at 469.3mw.
Keywords :
memory architecture; multiprocessing systems; multiprocessor interconnection networks; network-on-chip; parallel processing; storage allocation; 2-D block data processing; 64-core array system; block level matrix computation; digital signal processing platform design; frame data processing technology; hierachical architecture level; linear memory architecture; mirror symmetric interconnection structure; on chip addressing scheme design; on chip interconnection scheme; on chip structure scheme design; Arrays; Data processing; Matrix decomposition; Mirrors; Symmetric matrices; Throughput; 2-D data addressing; block data processing; matrix computation; mirror symmetric;
Conference_Titel :
VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4577-0171-9
Electronic_ISBN :
978-1-4577-0169-6
DOI :
10.1109/VLSISoC.2011.6081670
