Communication centric on-chip power grid models for networks-on-chip

Adverse effects of unreliable on-chip power supply delivery are exacerbated due to the rapid shrinking of device dimensions and the ever increasing power consumptions in nanometre-scale integration. Power supply integrity becomes a critical concern. Particularly, on-chip communication networks, such as networks-on-chip (NoC), dictates power dissipations and overall system performance in multi-core systems and emerging embedded computing architectures. These new communication centric architectures require dedicated power grid model that embeds distinctive communication characteristics and spatial parameters for analysing impacts of power supply voltage drop and noise. In this paper, we present a new on-chip power delivery model that captures the on-chip communication patterns and power grid dynamics. This model integrates cycle-accurate simulation of networks-on-chip to analyze the impact of different design entities on power supply noise. The model has been rigorously evaluated. Novel observations of power delivery integrity due to communication network design are presented. This model provides a unique and communication-centric perspective to analyse power supply integrity that leads to future robust and reliable multi-core system design.