A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources

In this work, we propose a fault-tolerant framework for Network on Chips (NoC) to achieve maximum performance under fault. A fine-grained fault model is first introduced. Different from the traditional link or node NoC fault models which assume the faulty resource to be totally unfunctional, we distinguish the faulty components and handle them according to their fault classes. By doing so, we can avoid unnecessary partitioning of the network and hence achieve a higher connectivity under high fault rate. Two new dynamic reconfiguration schemes at the router level, namely Dynamic Buffer Swapping (DBS) and Dynamic MUX Swapping(DMS), are proposed to deal with the buffer and cross-bar faults accordingly, which are the main sources of failure in the router. In these schemes, the healthy resources in the router are maximally utilized to mitigate the faults. Experimental results show that we can achieve higher packet acceptance rate and lower latency compared with state-of-the-art fault-tolerant routing schemes.