Statistical variability in n-channel UTB-FD-SOI MOSFETs under the influence of RDF, LER, MGG and PBTI

Statistical variability is a critical challenge to scaling and integration, affecting performance, leakage power, and reliability of devices, circuits, and systems. The UTB-FD SOI transistor-architecture dramatically reduces the statistical variability due to random dopant fluctuations (RDF), but other sources of variability remain pertinent, e.g. line edge roughness (LER), metal gate granularity (MGG) leading to work-function fluctuations, and interface trapped charge (ITC). The different physical nature of these phenomena affects the standard deviation and distribution of threshold voltage (V_TH) in different ways, and leads to a de-correlation with the on current (I_ON) of the transistor. These aspects have been extensively studied for ultra-scaled bulk-MOSFETs under various sources of variability experimentally or by physical device modelling, but have not been fully researched for FD-SOI devices a shortfall that this work aims to address.