DocumentCode :
2349224
Title :
DfT Architecture for 3D-SICs with Multiple Towers
Author :
Chi, Chun-Chuan ; Marinissen, Erik Jan ; Goel, Sandeep Kumar ; Wu, Cheng-Wen
fYear :
2011
fDate :
23-27 May 2011
Firstpage :
51
Lastpage :
56
Abstract :
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting of a single "tower", i.e., a 3D-SIC in which each stack level contains exactly one die. 3D stacking technology allows to place multiple dies on top of a common base die, resulting in 3D-SICs with multiple "towers". This paper presents a generic DfT architecture for 3D-SICs having any number of "towers", possibly including "sub-towers". We also present efficient test control mechanisms. Experimental results show that the proposed architecture has a negligible area cost for medium-sized and larger industrial designs, and therefore provides a cost-effective test solution for 3D-SICs.
Keywords :
design for testability; stacking; three-dimensional integrated circuits; 3D stacking technology; 3D-SIC; DfT architecture; cost effective test solution; design for testability; multiple tower; three-dimensional stacked IC; through silicon vias; Computer architecture; Equations; Logic gates; Multiplexing; Poles and towers; Testing; Wires; 3D-SIC; DfT; TSV; design-for-test; multi-tower; three-dimensional stacking; through-silicon via; wrapper;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ETS), 2011 16th IEEE European
Conference_Location :
Trondheim
ISSN :
1530-1877
Print_ISBN :
978-1-4577-0483-3
Electronic_ISBN :
1530-1877
Type :
conf
DOI :
10.1109/ETS.2011.52
Filename :
5957922
Link To Document :
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