Title :
Ultra-thin SOI for 20nm node and beyond
Author :
Aulnette, C. ; Schwarzenbach, W. ; Daval, N. ; Bonnin, O. ; Nguyen, B.-Y. ; Mazure, C. ; Maleville, C. ; Cheng, K. ; Ponoth, S. ; Khakifirooz, A. ; Hook, T. ; Doris, B.
Author_Institution :
SOITEC, Bernin, France
Abstract :
Recent UTBB device data at sub-25 nm gate length demonstrate good performance, small VT variation and excellent low power operation. In addition, very uniform Soitec Xtreme SOI™ product substrates are now available and compliant with device requirements. Thus the level of maturity of UTBB devices and substrates makes it possible for introduction at 20 nm node. Multiple options at the substrate level to further boost the performance open up the path to improve performance for future nodes.
Keywords :
performance evaluation; semiconductor devices; silicon-on-insulator; substrates; UTBB device data; device requirement; gate length; low power operation; size 20 nm; substrate level; ultra-thin SOI; very uniform Soitec Xtreme SOI product substrate; Logic gates; Manufacturing; Performance evaluation; Silicon; Substrates; Thickness measurement; Tuning;
Conference_Titel :
SOI Conference (SOI), 2011 IEEE International
Conference_Location :
Tempe, AZ
Print_ISBN :
978-1-61284-761-0
Electronic_ISBN :
1078-621X
DOI :
10.1109/SOI.2011.6081690
