Predictive State-Space for on-Chip Crosstalk Noise

Decreasing feature sizes to deep sub-micrometer (DSM) dimensions offers a large number of advantages for electronic devices such as high functional integration, reduced size and improvement in performance. However, designing at the DSM level brought with it challenges to -among others -crosstalk and delay techniques. The use of high clock frequencies, coupled with a large number of longer interconnect wires -of small cross section -packed closer together, gives rise to significant inductive coupling between on-chip interconnects. Therefore, for accurate modelling of crosstalk noise, the inductive and distributed nature of on-chip interconnects have to be properly modelled. In this paper, a state-space-based analytical model for crosstalk noise estimation is presented. The model can also assist in predicting the effect of crosstalk on circuit parameters.