Title :
Design and optimization of a 5 GHz CMOS power amplifier
Author :
Ko, Yus ; Eisenstadt, William R. ; Paviol, James R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
Abstract :
RF CMOS power amplifier is designed for WLAN 802.11a applications. The fully integrated differential power amplifier, operating in the 5-6 GHz bands, is implemented in a 0.18 μm IBM 7WL BiCMOS SiGe process using CMOS transistors. This process has seven metal layers and thin-oxide metal-metal capacitors, which are high density. As a result, the chip size as well as the cost of the complete power amplifier is reduced. The configuration of the power amplifier is a three-stage cascaded structure with a common source-common gate cascode and a 3.3 V supply voltage. The packaged power amplifier with bondwire and package models has a 22.8 dBm P1dB compression output power with a 24.1 dBm saturation output power, an overall power added efficiency of 22.6%, and a power gain of 30 dB in simulation.
Keywords :
BiCMOS analogue integrated circuits; CMOS analogue integrated circuits; MMIC power amplifiers; circuit optimisation; integrated circuit design; semiconductor materials; silicon compounds; wireless LAN; 0.18 mum; 3.3 V; 30 dB; 5 to 6 GHz; BiCMOS SiGe process; CMOS transistors; RF CMOS power amplifier; SiGe; WLAN 802.11a applications; common source-common gate cascode; integrated differential power amplifier; metal layers; optimization; thin-oxide metal-metal capacitors; three-stage cascaded structure; BiCMOS integrated circuits; Design optimization; Differential amplifiers; Packaging; Power amplifiers; Power generation; Radio frequency; Radiofrequency amplifiers; Silicon germanium; Wireless LAN;
Conference_Titel :
Wireless and Microwave Technology, 2005. WAMICON 2005. The 2005 IEEE Annual Conference
Print_ISBN :
0-7803-8861-5
DOI :
10.1109/WAMIC.2005.1528356
