• DocumentCode
    2349450
  • Title

    An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration

  • Author

    Neophytou, Stelios ; Christou, Kyriakos ; Michael, Maria K.

  • Author_Institution
    Electr. & Comput. Eng. Dept., Univ. of Nicosia, Nicosia, Cyprus
  • fYear
    2011
  • fDate
    23-27 May 2011
  • Firstpage
    141
  • Lastpage
    146
  • Abstract
    The correlation between the physical paths of a digital circuit has important implications in various design automation problems, such as timing analysis, test generation and diagnosis. When considering the complexity and tight timing constraints of modern circuits, this correlation affects both the design process and the testing approaches followed in manufacturing. In this work we quantify the diversity of a set of paths (or path segments), let these be critical I/O paths, error propagation paths for various fault models, or paths traced for diagnostic purposes. Circuit paths are encoded using Zero-Suppressed Binary Decision Diagrams (ZBDDs), the proposed method consists of a sequence of standard ZBDD operations to provide a measure of the overlap of the paths under consideration. The main contribution of the presented method is that, path or path segment enumeration is entirely avoided and, hence, a large number of paths can be considered in practical time. Experimentation using standard benchmark circuits demonstrates the effectiveness of the approach in showing the difference in path correlation between various critical I/O path sets.
  • Keywords
    digital integrated circuits; integrated circuit design; integrated circuit testing; ZBDD; benchmark circuits; digital circuits; error propagation paths; fault models; path correlation quantification; path enumeration; segment enumeration; test diagnosis; test generation; timing analysis; zero-suppressed binary decision diagrams; Arrays; Circuit faults; Correlation; Delay; Histograms; Integrated circuit modeling; Logic gates; digital circuits; path similarity; zero-supressed binary decision diagrams;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium (ETS), 2011 16th IEEE European
  • Conference_Location
    Trondheim
  • ISSN
    1530-1877
  • Print_ISBN
    978-1-4577-0483-3
  • Electronic_ISBN
    1530-1877
  • Type

    conf

  • DOI
    10.1109/ETS.2011.44
  • Filename
    5957937