• DocumentCode
    2349607
  • Title

    Anomalous floating-body effects in SOI MOSFETs: Low-voltage CMOS?

  • Author

    Fossum, Jerry G. ; Lu, Zhichao

  • Author_Institution
    Univ. of Florida, Gainesville, FL, USA
  • fYear
    2011
  • fDate
    3-6 Oct. 2011
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    The anomalous DC pseudo-latch of S4 MOSFETs was physically explained via UFPDB simulations, and a different, fast-transient pseudo-latch in FD/SOI S4 MOSFETs was demonstrated and explained. The transient latch tends to occur in PD/SOI S4 MOSFETs as well, but with different properties. We conclude that S4 MOSFETs for fast, low-voltage nanoscale CMOS warrant more study. We stress that S4 CMOS operation is novel, and thus in need of optimal (device and circuit) design as well as resolution of issues like hysteresis.
  • Keywords
    CMOS integrated circuits; MOSFET; low-power electronics; silicon-on-insulator; S4 CMOS operation; SOI MOSFET; UFPDB simulation; anomalous DC pseudo-latch; anomalous floating-body effects; fast-transient pseudo-latch; low-voltage CMOS; low-voltage nanoscale CMOS; transient latch; CMOS integrated circuits; Digital video broadcasting; Hysteresis; Latches; Logic gates; MOSFETs; Transient analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference (SOI), 2011 IEEE International
  • Conference_Location
    Tempe, AZ
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-61284-761-0
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2011.6081703
  • Filename
    6081703
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2349607