Anomalous floating-body effects in SOI MOSFETs: Low-voltage CMOS?

The anomalous DC pseudo-latch of S4 MOSFETs was physically explained via UFPDB simulations, and a different, fast-transient pseudo-latch in FD/SOI S4 MOSFETs was demonstrated and explained. The transient latch tends to occur in PD/SOI S4 MOSFETs as well, but with different properties. We conclude that S4 MOSFETs for fast, low-voltage nanoscale CMOS warrant more study. We stress that S4 CMOS operation is novel, and thus in need of optimal (device and circuit) design as well as resolution of issues like hysteresis.