• DocumentCode
    2349614
  • Title

    Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional Failures

  • Author

    Fang, Hongxia ; Wang, Zhiyuan ; Gu, Xinli ; Chakrabarty, Krishnendu

  • Author_Institution
    ECE Dept, Duke Univ., Durham, NC, USA
  • fYear
    2011
  • fDate
    23-27 May 2011
  • Firstpage
    195
  • Lastpage
    200
  • Abstract
    Despite recent advances in structural test methods, the diagnosis of the root cause of board-level failures for functional tests remains a major challenge. A promising approach to address this problem is to carry out fault diagnosis in two phases -- suspect faulty components on the board or modules within components (together referred to as blocks in this paper) are first identified and ranked, and then fine-grained diagnosis is used to target the suspect blocks in ranked order. We propose a new method based on dataflow analysis and Dempster-Shafer theory for ranking faulty blocks in the first phase of diagnosis. The proposed approach transforms the information derived from one functional test failure into multiple-stage failures by partitioning the given functional test into multiple stages. A measure of "belief" is then assigned to each block based on the knowledge of each failing stage, and Dempster-Shafer theory is subsequently used to aggregate the beliefs from multiple failing stages. Blocks with higher beliefs are ranked at the top of the candidate list. Simulations on an industry design for a network interface application show that the proposed method can provide accurate ranking for most board-level functional failures.
  • Keywords
    electronic engineering computing; fault diagnosis; inference mechanisms; modules; network interfaces; printed circuit testing; uncertainty handling; Dempster-Shafer theory; board level functional failure diagnosis; dataflow analysis; fault diagnosis; faulty blocks; fine grained diagnosis; functional test failure; network interface application; Clocks; Computational modeling; Industries; Logic gates; Monitoring; Registers; Transient analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium (ETS), 2011 16th IEEE European
  • Conference_Location
    Trondheim
  • ISSN
    1530-1877
  • Print_ISBN
    978-1-4577-0483-3
  • Electronic_ISBN
    1530-1877
  • Type

    conf

  • DOI
    10.1109/ETS.2011.23
  • Filename
    5957946