Novel architecture to boost the vertical tunneling in Tunnel Field Effect Transistors

A novel architecture to boost the performance of the Tunnel Field Effect Transistor is proposed. The improvement of drive current and subthreshold swing is achieved by inserting the channel between the source region and the gate dielectric, confining the electric field in the undoped channel region. The main feature of this architecture is to boost the vertical tunneling while suppressing the lateral tunneling path responsible for the degradation of the subthreshold swing.