A resilient 3-D stacked multicore processor fabricated using die-level 3-D integration and backside TSV technologies

Author

Lee, Ki-Won ; Hashimoto, Hiroya ; Onishi, M. ; Sato, Yuuki ; Murugesan, Mariappan ; Bea, J.-C. ; Fukushima, Tetsuya ; Tanaka, T. ; Koyanagi, Mitsumasa

Author_Institution

New Ind. Creation Hatchery Center (NICHe), Tohoku Univ., Sendai, Japan

fYear

2014

fDate

27-30 May 2014

Firstpage

304

Lastpage

308

Abstract

A highly dependable 3-D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed. The prototype 3-D stacked multicore processor with two layer structure is implemented using die-level 3-D integration and backside Cu TSV technologies. The basic functions of tier boundary scan and self-repair circuits via TSVs between each layer in the 3-D stacked multicore processor are successfully evaluated. X-ray computed tomography (X-ray CT) scanning technology is proposed as a nondestructive failure analysis method to characterize high-density TSVs integration, and bump joining qualities in the 3-D stacked multicore processor.

Keywords

automatic testing; computerised tomography; copper; failure analysis; multiprocessing systems; three-dimensional integrated circuits; Cu; X-ray CT; X-ray computed tomography; area-efficient TSV repair; backside Cu TSV technologies; bump joining qualities; die-level 3D integration; nondestructive failure analysis; resilient 3D stacked multicore processor; scanning technology; self-repair circuits; self-repair functions; self-test functions; tier boundary scan circuits; two layer structure; Built-in self-test; Maintenance engineering; Metals; Multicore processing; Optimization; Silicon; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th

Conference_Location

Orlando, FL

Type

conf

DOI

10.1109/ECTC.2014.6897303

Filename

6897303