A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture

Input vector monitoring concurrent Built-In Self-Test (BIST) schemes can circumvent problems appearing separately in on-line and off-line BIST techniques. The concurrent test latency of an input vector monitoring concurrent BIST scheme is the time required in order to complete the concurrent test. In this paper a novel input vector monitoring concurrent BIST scheme is presented. The proposed BIST scheme is shown to have lower hardware overhead for the same values of the concurrent test latency compared to previously proposed schemes.