DocumentCode :
234978
Title :
Development of new 2.5D package with novel integrated organic interposer substrate with ultra-fine wiring and high density bumps
Author :
Oi, Kumiko ; Otake, Satoshi ; Shimizu, N. ; Watanabe, Shigetaka ; Kunimoto, Yusuke ; Kurihara, Takashi ; Koyama, Tomofumi ; Tanaka, Mitsuru ; Aryasomayajula, Lavanya ; Kutlu, Zafer
Author_Institution :
R&D Div., Shinko Electr. Ind. Co., Ltd., Nagano, Japan
fYear :
2014
fDate :
27-30 May 2014
Firstpage :
348
Lastpage :
353
Abstract :
2.5D packaging technology utilizing silicon interposers is being developed and used for high-performance applications as the demand for miniaturization and higher density continues to increase. Silicon interposers enable very high density interconnects using standard semiconductor fabrication process technology, but are challenged as size increases. An alternative solution, high density laminate interposer, can offer advantages in cost, form factor, and infrastructure over other interposer options available today. However, it is difficult to manufacture high density wiring and flip chip bump pads on laminate interposer because conventional build-up technology limits fine line and via diameter. Our solution is the combination of an integrated organic interposer substrate with high density interconnects and thermo-compression flip chip bonding. Our solution eliminates the backside integration process for silicon interposer and assembly of interposers onto substrates. Conventional assembly processes can be utilized for assembling dies onto the integrated organic interposer substrate. Feasibility of this 2.5D package has been demonstrated by assembling dual-die with 40um pitch copper pillar bumps onto this novel integrated organic interposer substrate with 2μm line and space.
Keywords :
flip-chip devices; integrated circuit interconnections; lead bonding; 2.5D packaging technology; backside integration process; dual-die; flip chip bump pads; high density laminate interposer; high density wiring; integrated organic interposer substrate; pitch copper pillar bumps; semiconductor fabrication process technology; silicon interposers; size 2 mum; size 40 mum; thermocompression flip chip bonding; very high density interconnects; Bonding; Bonding forces; Copper; Flip-chip devices; Soldering; Substrates; Surface finishing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location :
Orlando, FL
Type :
conf
DOI :
10.1109/ECTC.2014.6897310
Filename :
6897310
Link To Document :
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