Asynchronous ADC with configurable resolution and binary tree structure

An Analogue to Digital Converter (ADC) implemented in CMOS technology (90nm TSMC) is described in this paper which is based on a binary tree structure and has a configurable 4, 8 or 12-bits resolution. The function performed at the nodes of the binary tree is an integer division by a proper power of 2, that is implemented by a novel circuit. The developed ADC system is an asynchronous circuit operating in current mode needing only a small number of components. This fact in conjunction with the binary tree structure of the ADC architecture, lead to implementations with very low die area and power consumption (0.12mm2 and 72mW respectively for 12-bit resolution). The average sampling rate exceeds 140MS/s for 12-bit resolution. The proposed device can also be used in multi Gbps time-interleaved parallel ADC due to its very low die area and power consumption.