DocumentCode
2349817
Title
A Low-Cost Emulation System for Fast Co-verification and Debug
Author
Lagos-Benites, J. ; Grosso, M. ; Sterpone, L. ; Reorda, M. Sonza ; Audisio, G. ; Pipponzi, M. ; Sabatini, M.
Author_Institution
DAUIN, Politec. di Torino, Torino, Italy
fYear
2011
fDate
23-27 May 2011
Firstpage
212
Lastpage
212
Abstract
A flexible system for SoC co-verification is proposed, built around an Infrastructure Microprocessor (IM), providing improved controllability and observability in a fast self-contained FPGA-based emulation environment. In addition, software debug is supported by enabling observation of critical signals, breakpoint setting and step-by-step execution with total memory accessibility. Experimental results in an industrial case study confirm the effectiveness of the approach for validating and debugging hardware and software.
Keywords
VLSI; embedded systems; field programmable gate arrays; formal verification; system-on-chip; breakpoint setting; critical signals; debug; fast co-verification; infrastructure microprocessor; low-cost emulation system; step-by-step execution; total memory accessibility; Conferences; Emulation; Field programmable gate arrays; Hardware; Random access memory; Software; Tires; FPGA; System-on-Chip; co-verification; debug;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ETS), 2011 16th IEEE European
Conference_Location
Trondheim
ISSN
1530-1877
Print_ISBN
978-1-4577-0483-3
Electronic_ISBN
1530-1877
Type
conf
DOI
10.1109/ETS.2011.32
Filename
5957958
Link To Document