Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors

A recent work showed that g_D of long-channel self-cascode transistors can be further reduced by replacing M₂ with a transistor with intrinsic concentration in the channel. In order to extend this proposal to more recent technologies, the current work presents an analysis of short-channel asymmetric self-cascode transistors implemented using a multi-threshold voltage commercial process. Numerical simulations were also performed aiming to extend the study, searching for the optimal doping concentration and length for M₁ and M₂.