Title :
Enhancement of Clock Delay Faults Testing
Author :
Higami, Yoshinobu ; Takahashi, Hiroshi ; Kobayashi, Shin-ya ; Saluja, Kewal K.
Author_Institution :
Grad. Sch. of Sci. & Eng., Ehime Univ., Matsuyama, Japan
Abstract :
This paper addresses the problem of simultaneous presence of multiple faults consisting of clock delay and gate transitions faults. The conditions of detecting a target multiple fault are converted into those for detecting a single stuck-at fault by adding some logic during the ATPG process. Experimental results show the effectiveness of our method by achieving nearly 100% fault efficiency.
Keywords :
automatic test pattern generation; delays; fault diagnosis; logic testing; object detection; ATPG process; clock delay fault testing; gate transition fault; stuck-at fault; target multiple fault detection; Automatic test pattern generation; Benchmark testing; Circuit faults; Clocks; Delay; Integrated circuit modeling; Logic gates; Clock line; Delay faults; Test Generation;
Conference_Titel :
Test Symposium (ETS), 2011 16th IEEE European
Conference_Location :
Trondheim
Print_ISBN :
978-1-4577-0483-3
Electronic_ISBN :
1530-1877
DOI :
10.1109/ETS.2011.27
