DocumentCode :
2349939
Title :
Comparative study of tri-gate flash memories with split and stack gates
Author :
Kamei, T. ; Liu, Y.X. ; Matsukawa, T. ; Endo, K. ; O´uchi, S. ; Tsukada, J. ; Yamauchi, H. ; Ishikawa, Y. ; Hayashida, T. ; Sakamoto, K. ; Ogura, A. ; Masahara, M.
Author_Institution :
Sch. of Sci. & Technol., Meiji Univ., Kawasaki, Japan
fYear :
2011
fDate :
3-6 Oct. 2011
Firstpage :
1
Lastpage :
2
Abstract :
The functional tri-gate flash memories with split gate have been demonstrated for the first time, and its Vt variabilities before and after one P/E cycle have be systimetically compared with stack-gate ones. It was confirmed that split-gate shows smaller V, distribution after erase and excellent over-erase immunity compared to those of stack-gate. Moreover, it was found that BVDS is higher than 3.2 V even Lgc was down to 76 nm. This indicates that tri-gate is useful for scaled NOR flash.
Keywords :
flash memories; logic gates; functional tri-gate flash memories; scaled NOR flash; split gates; stack gates; Fabrication; Logic gates; Split gate flash memory cells; Three dimensional displays; Transistors; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference (SOI), 2011 IEEE International
Conference_Location :
Tempe, AZ
ISSN :
1078-621X
Print_ISBN :
978-1-61284-761-0
Electronic_ISBN :
1078-621X
Type :
conf
DOI :
10.1109/SOI.2011.6081721
Filename :
6081721
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2349939
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