Title :
Banked scratch-pad memory management for reducing leakage energy consumption
Author :
Kandemir, M. ; Irwin, M.J. ; Chen, G. ; Kolcu, I.
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. We propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into low-power (low-leakage) state.
Keywords :
circuit layout CAD; circuit optimisation; integrated circuit layout; memory architecture; program compilers; SPM bank idleness; banked scratch-pad memory management; compiler-based leakage energy optimization; compiler-guided data layout optimization; data migration; leakage energy consumption reduction; low-leakage SPM bank; low-power SPM bank; on-chip scratch-pad memories; Cache memory; Decoding; Energy consumption; Energy management; Hardware; Logic; Memory management; Optimizing compilers; Runtime; Scanning probe microscopy;
Conference_Titel :
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
Print_ISBN :
0-7803-8702-3
DOI :
10.1109/ICCAD.2004.1382555
