An enhanced power integrity analysis flow based on the interdependence between simultaneous switching output noise and static IR drop

This paper presents an in-depth study on how the magnitude of simultaneous switching output (SSO) noise is affected by on-chip supply grid resistances. A key observation of the study is that under certain circumstances, increasing the resistance of certain parts of a supply grid can be very effective in reducing SSO noise, and the gain from SSO noise reduction can significantly outweigh the resulted increase in static IR drop. Based on this observation, an enhanced power integrity analysis flow is proposed for high speed interface design. Unlike conventional practices, our proposed flow considers SSO noise and static IR drop as two closely interrelated issues, and addresses them in a co-design manner throughout the design process.