Author :
Hu, Yu Hen ; Liu, C.S. ; Chen, M.T. ; Cheng, M.D. ; Kuo, H.J. ; Lii, M.J. ; La Manna, A. ; Rebibis, Kenneth June ; Wang, Tao ; Huylenbroeck, S.V. ; Daily, R. ; Capuz, G. ; Velenis, Dimitrios ; Beyer, G. ; Beyne, Eric ; Yu, Doug C. H.
Abstract :
We demonstrate for the first time 3D multi-tier (N=4) 50μm thin die bonding for 3D IC technology using low bonding temperature and pressure for Cu TSVs bonded on Cu bumps with a cost effective structure. Die-to-die (D2D) thermal compression bonding (TCB) process with scrubbing is carefully studied in order to improve the bump height TTV and surface roughness. The bonding temperature and pressure can also be reduced significantly to below 220C and 100MPa. The standalone thin die warpage initially 15μm is reduced to 5.4μm by applying the optimized TCB process. The electrical characterizations show good daisy chain connections between each stacked chip and the resistances are very close to the theoretical values. The cross section SEM proofs good TSV alignment to Cu bump, and TSV nails deform and land nicely onto the Cu bump. Finally, we propose to move forward to die-to-wafer approach and migrate to 10μm bump pitch for advanced package application.
Keywords :
integrated circuit bonding; integrated circuit packaging; microassembling; three-dimensional integrated circuits; 3D IC technology; Cu; D2D process; TCB process; TSV alignment; advanced package application; bump height TTV; bump pitch migration; cost effective structure; cross section SEM proofs; daisy chain connections; die-to-die process; die-to-wafer approach; electrical characterizations; low bonding pressure; low bonding temperature; multitier thin die bonding; process development; size 50 mum; standalone thin die warpage; surface roughness; thermal compression bonding process; through-silicon via; Bonding; Force; Nails; Stacking; Surface treatment; Three-dimensional displays; Through-silicon vias;
