A parallel implementation of the ISO 8802-2.2 protocol

Author

Iserswerth, Matthias Ka

Author_Institution

IBM Zurich Res. Lab., Switzerland

fYear

1991

fDate

18-19 Apr 1991

Firstpage

75

Lastpage

88

Abstract

A parallel implementation of the ISO 8802-2.2 Logical Link Control protocol on a multiprocessor-based communication adapter is described. Detailed measurements allow the authors to construct and parameterize a model of the implementation. The model shows how pipelining of different protocol functions is possible and what performance gain can be expected when running the implementation on different processor configurations. The performance of the parallel implementation is more than 16000 information protocol data units per second, commensurate with emerging high-speed networks operating in the 100 Mb/s range

Keywords

computer networks; protocols; standards; ISO 8802-2.2 protocol; Logical Link Control; multiprocessor-based communication adapter; parallel implementation; performance gain; Communication system control; High-speed networks; ISO standards; Laboratories; Network interfaces; Pipeline processing; Predictive models; Program processors; Protocols; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications Software, 1991, 'Communications for Distributed Applications and Systems', Proceedings of TRICOMM '91., IEEE Conference on

Conference_Location

Chapel Hill, NC

Print_ISBN

0-87942-649-7

Type

conf

DOI

10.1109/TRICOM.1991.152878

Filename

152878