DocumentCode :
235063
Title :
TSV reliability model under various stress tests
Author :
Ben-Je Lwo ; Frank ; Lin, M.-S. ; Kuo-Hsin Huang
Author_Institution :
Dept. of Mechatron., Energy & Aerosp. Eng., Nat. Defense Univ., Taoyuan, Taiwan
fYear :
2014
fDate :
27-30 May 2014
Firstpage :
620
Lastpage :
624
Abstract :
Through Silicon Via (TSV) is the key technology for the 2.5D and 3D packaging, but reliability evaluations on the new technology products are limited because of the complexity of the environmental issues. To this end, reliability experiments on self-design TSV samples under combinations of several different environmental variables were proposed and performed in this study. The Weibull distribution model was next employed for reliability analyses and the parameters for each of the experimental results were extracted. After analyzing the Weibull parameters, factors that accelerate TSV unreliability are compared with discussions. This paper finally presents failure analyses through OM/SEM observations.
Keywords :
Weibull distribution; failure analysis; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; three-dimensional integrated circuits; 2.5D packaging; 3D packaging; OM observations; SEM observations; TSV reliability model; Weibull distribution model; failure analyses; reliability evaluations; stress tests; through silicon via; Aging; Electrical resistance measurement; Reliability; Resistance; Standards; Temperature measurement; Through-silicon vias; Reliability; Stress Test; TSV (Through Silicon Via);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location :
Orlando, FL
Type :
conf
DOI :
10.1109/ECTC.2014.6897350
Filename :
6897350
Link To Document :
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