Automatic translation of behavioral testbench for fully accelerated simulation

This work presents the automated process of translating behavioral testbench into synthesizable one for the hardware-accelerated simulation. Testbench is mainly implemented in unsynthesizable HDL description such as time delay, event control, non-static loops and sequential statements. Nonetheless, FPGA-based accelerator is limited to synthesizable design. To apply hardware acceleration to behavioral testbench, the proposed method automatically translates testbench into equivalent hardware by emulating the standard simulation reference model. By mapping testbench into hardware accelerator to be merged with the design under verification, we can accelerate behavioral testbench and remove the communication overhead between the software simulator and hardware accelerator. Our experiments demonstrated that the simulation time is reduced by a factor of about 1000 as compared to the conventional hardware accelerated simulation.