An effective design system for dynamically reconfigurable architectures

Author

Govindarajan, Sriram ; Ouaiss, Iyad ; Kaul, Meenakshi ; Srinivasan, Vinoo ; Vemuri, Ranga

Author_Institution

Cincinnati Univ., OH, USA

fYear

1998

fDate

15-17 Apr 1998

Firstpage

312

Lastpage

313

Abstract

The SPARCS system is an integrated partitioning and synthesis environment for reconfigurable architectures. In this paper, we use the Joint Photographic Experts Group (JPEG) image compression algorithm as a design example to demonstrate the effectiveness of dynamic reconfiguration achieved using SPARCS. We present a typical design process using the SPARCS system consisting of temporal partitioning, spatial partitioning, and design synthesis. The results, obtained on a commercial RC architecture, show that the multiply-reconfigured version of the JPEG compression algorithm achieves reasonable improvement in execution times compared to the one-time configured version

Keywords

data compression; field programmable gate arrays; image coding; reconfigurable architectures; JPEG image compression algorithm; SPARCS system; design synthesis; design system; dynamically reconfigurable architectures; integrated partitioning and synthesis environment; spatial partitioning; temporal partitioning; Algorithm design and analysis; Compression algorithms; Computer architecture; Discrete cosine transforms; Field programmable gate arrays; Image coding; Partitioning algorithms; Process design; Reconfigurable architectures; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-8900-5

Type

conf

DOI

10.1109/FPGA.1998.707932

Filename

707932