Title :
Coupling impact of single ended signals to LVDS interface
Author :
June Feng ; Chooi Ian Loh ; Lin, E. ; Du, Evason ; Guang Chen ; Oh, Dan
Author_Institution :
Altera Corp., San Jose, CA, USA
Abstract :
The speed of general purpose input output (GPIO) continues to increase as more consumer applications utilize “smart” devices. The low-voltage differential signaling (LVDS) is often times the highest speed that GPIO interface needs to support in the mixture of different single ended signaling pins. Although LVDS is differential and somewhat immune to direct signal coupling from other signals, it is still subject to coupling through a shared power supply noise. A thorough SSN analysis between single ended to differential signals is presented in this paper. To help designing GPIO systems, we have considered different single ended signaling types such as SSTL, LVTTL, etc.
Keywords :
field programmable gate arrays; integrated circuit noise; low-power electronics; network analysis; signalling; GPIO interface; LVDS interface; LVTTL signalling; SSN analysis; SSTL signalling; direct signal coupling; general purpose input output; low-voltage differential signaling; shared power supply noise; simultaneous switching noise; single ended signaling pins; Clocks; Couplings; Field programmable gate arrays; Integrated circuit modeling; Noise; Noise measurement; Pins;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location :
Orlando, FL
DOI :
10.1109/ECTC.2014.6897368
