Title :
A 3D analysis of source/drain capacitance in SOI MOSFET for practical circuit design
Author :
Kumagai, Kouichi ; Iwaki, Hiroaki ; Yoshino, Akira ; Kurosawa, Susumu
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
It is well known that the small capacitance of the source/drain (S/D) region in MOS/SOI devices is one of the most attractive characteristics for the circuit performance improvements. In order to perform the implementation of the three-dimensional (3D) effects of the S/D capacitance into circuit simulators for more precise simulations, it is strongly required to estimate 3D dependence of the S/D capacitance on transistor layout patterns. However, such effects of the 3D coupling between the adjacent S/D regions have not been investigated in detail. In this study, we analyzed 3D effects of the S/D capacitance in MOS/SOI devices using in-house simulators, and discussed the contribution of the 3D effects on the total S/D capacitance
Keywords :
MOSFET; capacitance; circuit analysis computing; digital simulation; electronic engineering computing; semiconductor device models; silicon-on-insulator; 3D analysis; 3D coupling; MOS/SOI devices; SOI MOSFET; Si; circuit design; circuit simulators; source/drain capacitance; three-dimensional effects; transistor layout patterns; Analytical models; Circuit optimization; Circuit simulation; Circuit synthesis; Coupling circuits; Laboratories; MOSFET circuits; National electric code; Parasitic capacitance; Ultra large scale integration;
Conference_Titel :
SOI Conference, 1994 Proceedings., 1994 IEEE International
Conference_Location :
Nantucket, MA
Print_ISBN :
0-7803-2406-4
DOI :
10.1109/SOI.1994.514206
