Floorplan design for multi-million gate FPGAs

Modern FPGAs have multi-millions of gates and future generations of FPGA will be even more complex. This means floorplanning tools will soon be extremely important for the physical design of FPGAs. Due to the heterogeneous logic and routing resources on an FPGA, FPGA floorplanning is very different from the traditional floorplanning for ASICs. This work presents the first FPGA floorplanning algorithm targeted for FPGAs with heterogeneous resources (e.g., Xilinx´s Spartan3 chips consisting of columns of CLBs, RAM blocks, and multiplier blocks). Our algorithm can generate floor-plans for Xilinx´s XC3S5000 architecture (largest of the Spartan3 family) in a few minutes.