Viable deep-submicron FD/SOI CMOS design for low-voltage applications

Current interest in SOI is focused mainly on low-voltage/low-power digital CMOS applications requiring deep-submicron devices. For low-voltage operation, thin-film fully depleted (FD) SOI MOSFETs are superior to their non-fully depleted (NFD) counterparts in several regards, e.g., nearly ideal subthreshold slope, immunity to the floating-body kink effect (i.e., threshold reduction), and easily reduced short-channel effect, all of which enable, in principal, scaling of the threshold voltage for speed retention. There is concern though about the sensitivity of the FD/SOI MOSFET threshold voltage to the film thickness since the film must be very thin to assure the FD condition. Conversely, the NFD/SOI MOSFET offers good threshold voltage control. In this paper, we use physical SOI MOSFET models implemented in a circuit simulator (SOISPICE) to gain insights regarding design of deep submicron FD/SOI CMOS for low-voltage applications. We demonstrate that FD/SOI is viable, but that a hybrid FD/NFD technology might be the optimal design for operation at less than 2 volts