Title :
Implementation of processor cells for array algorithms on FPGAs
Author :
Vássanyi, István ; Erényi, István
Author_Institution :
KFKI Res. Inst. for Meas. & Comput. Tech., Budapest, Hungary
Abstract :
Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal “jigsaw tessellated” processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based processor arrays by the implementation results of two cellular image processing algorithms. The outlined concepts are being implemented in a placement-routing tool
Keywords :
cellular arrays; field programmable gate arrays; FPGA; array algorithms; cellular image processing algorithms; fine-grain array architectures; placement-routing tool; processor arrays; processor cells; Clocks; Cost function; Electronics packaging; Field programmable gate arrays; Hardware; Logic arrays; Programmable logic arrays; Proposals; Systolic arrays; Tiles;
Conference_Titel :
EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference
Conference_Location :
Prague
Print_ISBN :
0-8186-7487-3
DOI :
10.1109/EURMIC.1996.546364
