A heuristic for logical data buffer allocation in multicore platforms

Author

Ries, Benjamin ; Unger, Walter ; Odendahl, Maximilian ; Leupers, Rainer

Author_Institution

Dept. of Comput. Sci. I, RWTH Aachen Univ., Aachen, Germany

fYear

2014

fDate

5-7 Dec. 2014

Firstpage

1

Lastpage

2

Abstract

In the past memory allocation and communication between processors and memories in current MPSoC´s, due to the small design space, was not a big challenge. Through advanced MPSoC´s and improving techniques to interface Dynamic RAM (DRAM), allocation of logical data buffers to physical memories is no longer manageable manually. We present a heuristic for the mapping of logical data buffers to physical memories and the routing of data flows. Our heuristic use an approximation scheme to obtain an fractional solution, and randomized rounding. We evaluate our implementation for different values of e using representative data of the Long Term Evolution Standard.

Keywords

DRAM chips; approximation theory; buffer storage; multiprocessing systems; system-on-chip; DRAM; MPSoC; approximation scheme; fractional solution; interface dynamic RAM; logical data buffer allocation; long term evolution standard; memory allocation; multicore platform; physical memories; randomized rounding; Algorithm design and analysis; Approximation algorithms; Approximation methods; Bandwidth; Random access memory; Resource management; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Performance Computing and Communications Conference (IPCCC), 2014 IEEE International

Conference_Location

Austin, TX

Type

conf

DOI

10.1109/PCCC.2014.7017040

Filename

7017040