Loop Selection to Boost Thread Level Speculation Parallelism in Chip Multiprocessor Systems

A novel loop selection framework with cost evaluation to boost thread level speculation (TLS) parallelism in chip multiprocessor (CMP) systems is proposed in this paper. In order to improve the performance, a loop selection framework with the aid of TLS and profiling is added to reduce unnecessary loops parallelization for their low gains even losses under parallelization. A number of techniques for this parallelization based TLS are presented and results provided indicate the performance contribution on six SPEC CPU2000 benchmark applications. This TLS parallelization yielded an average 175% speedup on our three integer applications and an average 198% on our three floating point applications.