A Double or Triple Module Redundancy Model Exploiting Dynamic Reconfigurations

Majority voting is a commonly used approach to increase system reliability. Standard triple-module-redundancy (TMR) methods are frequently used in space applications. Using these methods, triple modules and voting circuits are implemented onto an application specific integrated circuit (ASIC) or an FPGA. When a single event upset occurs, the voting circuit neglects the failure value of a module receiving the single event upset and takes a correct value of the other two modules not receiving it. However, the triple-module implementation requires a large implementation area on VLSIs. Therefore, to reduce the area of TMR implementation, this paper presents a novel double or triple module redundancy (DTMR) method for dynamically reconfigurable devices using a design example of a state machine. Furthermore, this paper presents experimental results of the method using a highly reliable optically reconfigurable gate array.