The impact of device parameter variations on the frequency and performance of VLSI chips

The distance-correlated (continuous) within-die (WID) process variations of transistor parameters appears to be approximately scaling with process generations. Furthermore, shrinking clock cycles and the scaling of functional block dimensions in complex chips (e.g. CPUs), cause a shortening of interconnect distances. These effects mitigate correlated variations´ impact on delay changes across a die. Temperature has a small effect, and supply distribution can be well-understood and designed. Furthermore, uncorrelated (random) variations (e.g. RDF, & LER) currently have a small impact on speed-setting paths, and even multiplying their effect (as processes shrink), would not make them very significant. Coupled with methods for estimating the shift in the maximum operating frequency (F_max) of a die (due to variations), it is shown that variations will continue to have a small effect on product speeds through the mid-term future.