Title :
Digit-serial DSP library for optimized FPGA configuration
Author :
Lee, Hanho ; Sobelman, Gerald E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
This paper gives the digit-serial DSP libraries used to implement the digit-serial DSP architecture for field programmable gate arrays (FPGAs) and compares schematic-based FPGA design with design based on logic synthesis for digit-serial DSP libraries. It describes the design of digit-serial addition/subtraction, multiplication and delay elements and indicates also how digit-serial FIR filter can be implemented. The FPGA device utilization and critical path delay of digit-serial DSP libraries are calculated and described
Keywords :
FIR filters; adders; delays; digital signal processing chips; field programmable gate arrays; critical path delay; delay elements; digit-serial DSP architecture; digit-serial DSP library; digit-serial FIR filter; digit-serial addition/subtraction; field programmable gate arrays; logic synthesis; multiplication; optimized FPGA configuration; Arithmetic; Circuits; Delay; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Libraries; Process design; Programmable logic arrays; Throughput;
Conference_Titel :
FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-8900-5
DOI :
10.1109/FPGA.1998.707936
