A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA´s

Reconfigurable logic devices such as SRAM-based field programmable gate arrays (FPGAs) are nowadays increasingly popular thanks to their capability of implementing complex circuits with very short development time and for their high versatility in implementing different kind of applications, ranging from signal processing to the networking. The usage of reconfigurable devices in safety critical fields, such as space or avionics, require the adoption of specific fault tolerant techniques, like triple modular redundancy (TMR), in order to protect their functionality against radiation effects. While these techniques allow increasing the protection capability against radiation effects, they introduce several penalties to the design, particularly in terms of performances. In this paper, we present a novel design flow able to implement fault tolerant circuits on SRAM-based FPGAs while reducing the performance penalties. The flow is based on a placement algorithm ruled by topology heuristics and on a routing algorithm driven by a congestion graph able to remove the crossing errors domains. Experimental evaluations performed by means of timing analysis and static analysis on industrial-like case studies demonstrated that the proposed algorithm is able to improve the running frequency up to the 44% versus standard TMR-based techniques while maintaining complete fault tolerance capabilities.