A Software Defined Radio Architecture for a Regenerative Onboard processor

The possibility to adapt in-flight the behaviour of a space-based equipment to different operating conditions and/or new functional requirements is of paramount importance in the field of the commercial multimedia communications. In fact, in a satellite lifetime of 15 years, new standards may arise, the existing one may be upgraded, or the opportunity to introduce new added-value services may be considered by a satellite operator. The in-flight adaptability is particularly significant for an On-Board Processor (OBP) based on the signal regeneration: such kind of equipments, though offering excellent performances in terms of BER/PER, require an access protocol to exploit the communication resources and this condition is an heavy limitation to the OBP flexibility, usually perceived as a risk factor by a commercial satellite operator. The present paper describes a Regenerative OBP architecture which makes use of the SRAM-based FPGA technology to obtain a fully reconfigurable platform, where any functional block of the signal processing chain may be completely modified in-flight. Together with the OBP architecture, a procedure to perform an efficient and reliable payload reconfiguration is described. A prototype of the proposed OBP architecture, based on COTS devices, will be realized in the frame of an ESA/ESTEC contract.