TSV module optimization for high performance silicon interposer

Author

Cao, Austin ; Dinan, Thomas ; Zhuowen Sun ; Guilian Gao ; Uzoh, Cyprian ; Bong-Sub Lee ; Liang Wang ; Hong Shen ; Arkalgud, S.

Author_Institution

Invensas, Inc., San Jose, CA, USA

fYear

2014

fDate

27-30 May 2014

Firstpage

862

Lastpage

867

Abstract

This paper presents Invensas´ silicon interposer technology for heterogeneous chip integration. Various process module and integrated blocks were optimized for yield and high performance in the interposer. The modules under evaluation include TSV etch, barrier deposition, electrochemical plating, chemical mechanical polishing (CMP), temporary bonding, low temperature oxide (LTO) and low temperature polyimide (LTPI) passivation.

Keywords

chemical mechanical polishing; chip scale packaging; electroplating; elemental semiconductors; optimisation; passivation; silicon; three-dimensional integrated circuits; TSV etch; TSV module optimization; barrier deposition; chemical mechanical polishing; electrochemical plating; heterogeneous chip integration; high performance silicon interposer; low temperature oxide; low temperature polyimide passivation; silicon interposer technology; temporary bonding; Copper; Polyimides; Surface treatment; Temperature measurement; Through-silicon vias; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th

Conference_Location

Orlando, FL

Type

conf

DOI

10.1109/ECTC.2014.6897387

Filename

6897387