A New High-Level Reconfigurable Lossless Image Compression System for Space Applications

Author

Yu, Guoxia ; Vladimirova, Tanya ; Wu, Xiaofeng ; Sweeting, Martin N.

Author_Institution

Dept. of Electron. Eng., Univ. of Surrey, Guildford

fYear

2008

fDate

22-25 June 2008

Firstpage

183

Lastpage

190

Abstract

On board image data compression is an important feature of satellite remote sensing payloads. Reconfigurable intellectual property (IP) cores can enable change of functionality or modifications. A new and efficient lossless image compression scheme for space applications is proposed. In this paper, we present a lossless image compression IP core designed using AccelDSP, which gives users high level of flexibility. One typical configuration is implemented and tested on an FPGA prototyping board. Finally, it is integrated successfully into a system-on-chip platform for payload data processing and control.

Keywords

data compression; field programmable gate arrays; geophysical signal processing; image coding; industrial property; remote sensing; system-on-chip; FPGA; high-level reconfigurable lossless image compression system; onboard image data compression; payload data processing; reconfigurable intellectual property; satellite remote sensing payloads; space applications; system-on-chip platform; Data compression; Field programmable gate arrays; Image coding; Intellectual property; Payloads; Prototypes; Remote sensing; Satellites; System-on-a-chip; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Adaptive Hardware and Systems, 2008. AHS '08. NASA/ESA Conference on

Conference_Location

Noordwijk

Print_ISBN

978-0-7695-3166-3

Type

conf

DOI

10.1109/AHS.2008.56

Filename

4584272