DocumentCode
2351410
Title
Design optimisation for bipolar transistors on BESOI substrates
Author
Armstrong, G.A. ; French, W.D. ; Gamble, H.S.
Author_Institution
Northern Ireland Semicond. Res. Cenre, Queen´´s Univ., Belfast, UK
fYear
1994
fDate
3-6 Oct 1994
Firstpage
45
Lastpage
46
Abstract
A strongly applications oriented silicon integrated circuit process is being developed using direct wafer bonding. By bonding a silicon wafer to an oxidised silicon wafer, thin SOI material suitable for bipolar circuits can be produced without the need for epitaxial growth. A highly doped layer is implanted into the active silicon wafer to form a buried collector. This wafer is then inverted prior to bonding to an oxidised handle wafer. The active wafer is then subjected to precision grinding and polishing to give a final silcon layer thickness in the range one to three microns. After formation of etched trenches which are filled with dielectric, the substrates with in situ buried collector are ready for bipolar processing
Keywords
bipolar integrated circuits; grinding; integrated circuit technology; polishing; silicon-on-insulator; wafer bonding; BESOI substrates; bipolar processing; bipolar transistors; buried collector; direct wafer bonding; etched trenches; in situ buried collector; integrated circuit process; oxidised handle wafer; polishing; precision grinding; thin SOI material; Algorithm design and analysis; Bipolar transistors; Circuit simulation; Design optimization; Doping; Implants; Job shop scheduling; Poisson equations; Processor scheduling; Silicon on insulator technology;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 1994 Proceedings., 1994 IEEE International
Conference_Location
Nantucket, MA
Print_ISBN
0-7803-2406-4
Type
conf
DOI
10.1109/SOI.1994.514227
Filename
514227
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