Addressing Future Space Challenges using Reconfigurable Instruction Cell Based Architectures

Space exploration is evidence to the human desire to better understand our world and the universe that surrounds us. As NASA, ESA and other space agencies design and deploy missions to return to Moon and explore Mars and beyond, the realization is emerging that intelligent payloads must be developed that can respond to the uncertain surroundings autonomously. Space computation challenges have continuously increased in the last decade, and expected to increase further for future space missions. Rapid developments in semiconductor technologies have lead to progression in sensors technology and enormous increase in their capability and accuracy. Rich sensor data encourages researchers to investigate the addition of sophisticated and advanced algorithms in space vehicles to deal with the enormous amount of received data. This has increased the demand on the onboard processing capabilities. In addition, the new trend of shifting the data processing from on-ground to onboard has increased the request on the flexibility and adaptability for space processors. In this paper we discuss the possibility of applying the reconfigurable instruction cell architecture (RICA) in payload data processing. We propose a RICA based processor as a candidate for future space missions. A study of the suggested modifications for the RICA processor to meet future space computation challenges has also been discussed.