Title :
Wet silicon etch process for TSV reveal
Author :
Mauer, Laura B. ; Taddei, John ; Youssef, Rabaa ; Yongqiang Lu ; Collins, Stephen ; McLaughlin, Keiran ; Allen, Colin
Author_Institution :
Solid State Equip., LLC, Horsham, PA, USA
Abstract :
This paper presents a wet process as a simple and cost-effective alternative to the polish/plasma etch TSV reveal process. By combining silicon thickness measurement, wet etch, and cleaning in a single-wafer process system, this platform provides a low cost-of-ownership solution for TSV reveal. The process uses a wet etch chemistry with a fast etch rate and high selectivity, in a single-wafer process tool. The new selective etch chemistry improves the etch rate by 50% or more over traditional Si etchants currently used in the industry, such as tetramethylammonium hydroxide (TMAH). This new etch chemistry also has high silicon-etch selectivity over the oxide liner and Cu, with etch rate (ER) ratios greater than 10,000 and 1000, respectively. TMAH is not a component in the chosen chemistry because of safety concerns specifically related to TMAH toxicity. Variations in the depth of the Si overburden occur due to non-uniformities in post-grind thickness, via depth, and bonding. To compensate, an algorithm is used to control etch profiles. Integration of wafer thickness measurements before and after etching-within the single-wafer equipment-provides the high-accuracy process control needed for high-volume manufacturing. Improvement in surface roughness and etch uniformity are achieved with this wet process through the combination of chemistry performance and process optimization.
Keywords :
elemental semiconductors; integrated circuit manufacture; integrated circuit measurement; silicon; sputter etching; surface roughness; thickness measurement; three-dimensional integrated circuits; Si; TMAH toxicity; chemistry performance; cost-of-ownership solution; etch profiles; etch uniformity; fast etch rate; high-volume manufacturing; oxide liner; polish/plasma etch TSV reveal process; post-grind thickness; process control; process optimization; selective etch chemistry; silicon thickness measurement; silicon-etch selectivity; single-wafer equipment; single-wafer process system; single-wafer process tool; surface roughness; tetramethylammonium hydroxide; via depth; wafer thickness measurements; wet etch chemistry; wet silicon etch process; Chemicals; Rough surfaces; Silicon; Surface roughness; Surface treatment; Through-silicon vias;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location :
Orlando, FL
DOI :
10.1109/ECTC.2014.6897390