DocumentCode :
2351474
Title :
High performance submicron SOI devices with silicon film thickness below 50 nm
Author :
Raynaud, C. ; Faynot, O. ; Giffard, B. ; Gautier, J.
Author_Institution :
DMEL-CENG, LETI, Grenoble, France
fYear :
1994
fDate :
3-6 Oct 1994
Firstpage :
55
Lastpage :
56
Abstract :
Two different options are available for submicron SOI devices: one is to keep the silicon thickness relatively thick, about 100 nm, in using a complex architecture as for bulk devices; the second one is to reduce the silicon film thickness below 50nm for sub 0.25 μm devices, in order to obtain fully depleted devices. The main problem in this last case can be the dispersion of the electrical parameters due to a silicon thickness nonuniformity. But the benefits are the reduction of short channel effects, a better control of the impact ionization and the improvement of the subthreshold slope that allows lower threshold voltage values. The sensitivity to silicon thickness is not so severe in practice than it can be shown in theoretical simulations, due to a balance between the doping level and the silicon thickness for a constant implant dose, used for channel doping
Keywords :
MOSFET; doping profiles; elemental semiconductors; impact ionisation; semiconductor doping; silicon; silicon-on-insulator; 0.25 micron; Si; channel doping; constant implant dose; doping level; electrical parameter dispersion; fully depleted devices; impact ionization; short channel effects; submicron SOI devices; subthreshold slope; threshold voltage values; Doping; Impact ionization; Implants; MOSFETs; Oxidation; Semiconductor films; Silicon; Substrates; Threshold voltage; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 1994 Proceedings., 1994 IEEE International
Conference_Location :
Nantucket, MA
Print_ISBN :
0-7803-2406-4
Type :
conf
DOI :
10.1109/SOI.1994.514232
Filename :
514232
Link To Document :
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