Title :
Realization of a mixed-mode neural coprocessor for signal processing
Author :
Romariz, A.R.S. ; Ferreira, P.U.A. ; Campêlo, J.V., Jr. ; Graciano, M.L., Jr. ; Maia, O.R., Jr. ; da Costa, J.C.
Author_Institution :
Dept. de Engenharia Eletrica, Brasilia Univ., Brazil
Abstract :
A hybrid architecture for neural coprocessing is presented. A fixed set of analog multipliers and capacitors (analog memory) emulates multilayer perceptrons through digitally-controlled multiplexing. Parallelism is partially preserved, then, without direct analog implementation of the whole structure. Details of system VLSI implementation are given, along with simulation results that validate system cells design
Keywords :
CMOS integrated circuits; VLSI; analogue multipliers; mixed analogue-digital integrated circuits; multilayer perceptrons; multiplexing; neural chips; neural net architecture; signal processing; CMOS IC; VLSI; analog multipliers; digital multiplexing; hybrid architecture; mixed-mode neural coprocessor; multilayer perceptrons; signal processing; Analog memory; Capacitors; Concurrent computing; Coprocessors; Multilayer perceptrons; Neural networks; Neurons; Parallel processing; Pipelines; Signal processing;
Conference_Titel :
Neural Networks, 1998. Proceedings. Vth Brazilian Symposium on
Conference_Location :
Belo Horizonte
Print_ISBN :
0-8186-8629-4
DOI :
10.1109/SBRN.1998.731023
