Title :
Logical effort based technology mapping
Author :
Karandikar, Shrirang K. ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended to solve the load-distribution problem for circuits with fanout. On average, benchmark circuits mapped using our approach are 25.39% faster than the solutions obtained from SIS.
Keywords :
circuit optimisation; integrated circuit design; load distribution; logic design; circuit mapping; fanout-free circuits; library-based technology mapping; load-distribution problem; logical effort; Circuit synthesis; Contracts; Delay effects; Delay estimation; Equations; Libraries; Load modeling; Logic circuits; Noise measurement; Parasitic capacitance;
Conference_Titel :
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
Print_ISBN :
0-7803-8702-3
DOI :
10.1109/ICCAD.2004.1382611
