Enabling of Fan-Out WLP for more demanding applications by introduction of enhanced dielectric material for higher reliability

Market is requesting more and more IC packages capable to cope with more demanding reliability requirements, in order to meet customer increased expectations regarding functionality, size, power dissipation and cost. Miniaturization needs, in an increasing number of applications, accelerate the implementation of WLP (Wafer Level Packaging) even in market segments not using WLP by today. This requires more robust and more reliable WLP solution, where Fan-Out versions like eWLB (embedded Wafer Level Ball Grid Array) will play an emphasized role in terms of system integration and high density packaging. To address those expectations, the packaging construction, especially RDL (redistribution layer) and dielectric materials of eWLB, has to be further enhanced. This paper will present the development activities performed regarding dielectric material characterization and selection, process development, integration, validation, qualification and transfer into volume production. The eWLB products qualified at NANIUM high volume manufacturing line cover a wide range of package configurations, mainly in terms of package size and thickness, proving the capability of the improved material/process for eWLB technology platform. As result of this development, NANIUM enabled the eWLB technology to fulfill also the needs of more demanding applications and market segments. The new eWLB packages are exceeding 1.000 cycles in component level based Temperature Cycling Test (TCT -55^oC to 125°C) according to JEDEC JESD47 (condition B) and 500 to 1.000 cycles, in board level based Temperature Cycling on Board Test (TCoB -40^oC to 125 °C) according IPC-9701 (condition TC3). The paper will also show results from Drop Test according JEDEC JESD22-B111. Due to its nature eWLB FO-WLP implies specific properties and processing conditions to dielectric materials candidates, like curing temperature, shrinkage level and stress buffer capability as examples. A f- ll material characterization of main related properties was initially performed to support the selection of the best candidate. The introduction of this enhanced dielectric material required deep development of several process steps and optimization of its integration. New surface cleaning steps were tested, completely new lithography processing conditions were introduced, curing and drying steps were adapted and new AOI configuration was developed. Finally, specific test vehicles were designed and produced to test and validate the complete technology. This included all package and reliability tests according to JEDEC more stringent standards, like uHAST, THB, TCT, HTS, TCoB and Drop Test.